Stockton FabC Series S

D

C

B

A

STOCKTON FAB C MEMORY: PWR/VSS & DECAP, A SOC & Memory: CHA/PHY0 SOC: V_CPUCORE DECOUPLING REV 0.12 43 VREGS: V_12P0_GATED VREGS: INPUT DECOUPLING VREGS: V_CPUCORE, V_GFXCORE CONTROLLER VREGS: V_GFXCORE OUTPUT PHASE 1 & 2 VREGS: V_GFXCORE OUTPUT PHASE 3 & 4 47 52 CONN: POWER VREGS: V_CPUCORE OUTPUT 54 48 45 49 VREGS: V_SOC OUTPUT 41 42 44 46 50 51 53 CONN: ODD CONN: M.2 VREGS: V_MEMIO AND V_MEMPHY OUTPUT VREGS: V_MEMIO, V_MEMPHY, V_SOC SENSE CONN: FRONT PANEL, FAN, NEXUS VREGS: V_MEMIO, V_MEMPHY, V_SOC CONTROLLER SOC: V_MEMIO/V_MEMPHY DECOUPLING SOC: POWER: GFXCORE, MEMPHY, MISC SOC: POWER: VSS SOC: V_GFXCORE DECOUPLING SOC: DEBUG, SB SIGNALS, V_BAT, VOLTAGE SENSE 7 SOC POWER: MEMIO, CPUCORE, SOC NONE 8 6 2 3 4 5 9 11 12 13 14 10 SOC: VIDEO SOC: V_SOC DECOUPLING SOC: PCIEX,CLOCKS 1 SOC: POWER: VSS SHEET SHEET NAME SHEET SHEET NAME D C
MEMORY: PWR/VSS & DECAP, B SOC & Memory: CHB/PHY1 55 VREGS: V_5P0 18 16 15 17	MEMORY: PWR/VSS & DECAP, C SOC & Memory: CHC/PHY2	56 58 57	VREGS: V_SB1P8, V_SB1P1 VREGS: V_SOC1P8, V_DRAM1P8 VREGS: V_SOCPHY, V_FUSE
21 22	USB	62	I2C
23	PCIEX, SATA, VIDEO	63	DEBUG: MARGIN V_SOCPHY,V_SOC1P8, V_DRAM1P8
24	SMM UART, SPI, JTAG, GPIO	64	DEBUG: MONITOR M.2. CFEXPRESS DEBUG: MONITOR V_SOC1P8, V_SOCPHY, V_12P0, V_DRAM1P8
25	POWER (VSS)	65	DEBUG: FACET HEADER
29 28	CLOCKS, STRAPPING, POR PCIE 100MHZ SS	66 67	DEBUG: FTDI BUFF, USB, PWR DEBUG: FTDI BRIDGE
	PCIE 100MHZ NS	68	DEBUG: SWITCHES, LEDS
31 32	(LEGACY) CONTROLLER	71 70	DEBUG: HDT DEBUG: VR HEADERS, TEST POINTS, CONNECTORS
			LABELS AND MOUNTING
33	EMMC SPI FLASH SOC		STOCKTON_NEXUS BOM DEFINITIONS
	SPI FLASH		B2B CONN AND LABELS
	MEMORY: MEMORY:
		69
1. MSB RULES: 39 38 40	IS TOP TO BOTTOM WHEN POSSIBLE) WIFI USB (FRONT & REAR)		9. UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE 13.SUFFIX _EN FOR ENABLE 15.PWRGD FOR POWER GOOD 14.'CLK' FOR CLOCKS, 'RST' FOR RESETS 12.SUFFIX _P FOR P JUNCTION 10.SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
2.	PAGES=CHIP INTERFACES, TERMINATION, POWER, INPUTS ON LEFT, OUTPUTS ON RIGHT LSB CONN:	75 72 73 74
3. 37 36	LOAD SWITCHES VIDEO OUT RJ45, SPDIF, CFEXPRESS PREMIUM AND RETAIL ETHERNET		16.REV AND FAB ARE SET USING CUSTOM VARIABLES
20 34 30 35	MEMORY: PWR/VSS & DECAP, D SB: SB: SB: SMC	60 61	VREGS: V_3P3_GATED, V_3P3_CFX
			VREGS: V_1P1STBY, V_1P8STBY
	SB:
	SB:
26
27	SB: POWER SB: DECOUPLING
	SB:
	CLOCK:
	CLOCK:
	SB:
ORDER 4. AVOID 8. WHEN 5. LANED 7. 6.	HDMI:	76	NEXUS LED AND POWER SWITCH
	HDMI: CONN: AUDIO:
TO SUFFIX
			TOOLS>OPTIONS>VARIABLES
			4 5
CONN:
OF DECOUPLING USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS POSSIBLE: SIGNALS ARE GROUPED ON SYMBOLS (APPLIED V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
Tue Jun 25 13:39:30 2019 DRAWING
8 6 7

Table Caption: This table appears to be a section of a schematic or design document, detailing various components, power rails (VREGS), and connections (CONN) within a system labeled "STOCKTON FAB C". It is divided into several sheets, each focusing on different functional blocks like memory, SOC (System on Chip), and peripheral interfaces.

D

C

B

A

8

MXXXXXXX-001

Z

Z

415

I153

M1114629-001

414

I154

M1114629-001

8

31

31

38

38

38

38

41

41

41

41

23

23

23

23

NC

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

MATL

IC

EMPTY

REF_DES

U1

U1

PEX_SPARE_SOC_TP

PEX_SPARE_SOC_TN

PEX_ENET_SOC_TP_C

PEX_ENET_SOC_TN_C

PEX_L1_CFX_SOC_TP

PEX_L1_CFX_SOC_TN

PEX_L0_CFX_SOC_TP

PEX_L0_CFX_SOC_TN

PEX_L1_M2_SOC_TP

PEX_L1_M2_SOC_TN

PEX_L0_M2_SOC_TP

PEX_L0_M2_SOC_TN

PEX_L1_SB_SOC_TP_C

PEX_L1_SB_SOC_TN_C

PEX_L0_SB_SOC_TP_C

PEX_L0_SB_SOC_TN_C

29

29

IN

30

30

IN

IN

IN

7

7

P4

N4

U4

T4

Y4

W4

AC4

AB4

AE4

AF4

AJ4

AK4

AM4

AP4

AV7

AV8

IC

SPARKMAN2

P_GPP_RX7_P

1 OF 24

P_GPP_TX7_P

P_GPP_RX7_N

P_GPP_TX7_N

P_GPP_RX6_P

P_GPP_RX6_N

P_GPP_RX5_P

P_GPP_RX5_N

P_GPP_RX4_P

P_GPP_RX4_N

P_GPP_RX3_P

P_GPP_RX3_N

P_GPP_RX2_P

P_GPP_RX2_N

P_GPP_RX1_P

P_GPP_RX1_N

P_GPP_RX0_P

P_GPP_RX0_N

M1114629-001

BGA1303

SOC_PEX_SS_100M_CLKP

SOC_PEX_SS_100M_CLKN

SOC_PEX_NS_100M_CLKP

SOC_PEX_NS_100M_CLKN

W1

V1

AB1

AA1

N6

M6

T6

R6

W6

V6

AB6

AA6

AD6

AE6

AG6

AJ6

AL6

AM6

AT4

AT5

R3

P_GPP_TX6_P

P_GPP_TX6_N

P_GPP_TX5_P

P_GPP_TX5_N

P_GPP_TX4_P

P_GPP_TX4_N

P_GPP_TX3_P

P_GPP_TX3_N

P_GPP_TX2_P

P_GPP_TX2_N

P_GPP_TX1_P

P_GPP_TX1_N

P_GPP_TX0_P

P_GPP_TX0_N

PEX_CAL_VSS

SOC_BASE

U1

SPARKMAN2

CLKIN_P

2 OF 24

CLKIN_N

CLKIN_NOSS_P

CLKIN_NOSS_N

M1114629-001

BGA1303

DESCR.

PROCSR,SOC,SM,1304-BGA,SPARKMAN35 SOC_INCLUDE

BOM PROPERTY

PROCSR,SOC,SM,1304-BGA,SPARKMAN35 SOC_EMPTY

6

U1

6

IC

5

4

SOC: PCIEX,CLOCKS

PEX_SOC_SPARE_TP

PEX_SOC_SPARE_TN

PEX_SOC_ENET_TP

PEX_SOC_ENET_TN

PEX_L1_SOC_CFX_TP

PEX_L1_SOC_CFX_TN

PEX_L0_SOC_CFX_TP

PEX_L0_SOC_CFX_TN

PEX_L1_SOC_M2_TP

PEX_L1_SOC_M2_TN

PEX_L0_SOC_M2_TP

PEX_L0_SOC_M2_TN

PEX_L1_SOC_SB_TP

PEX_L1_SOC_SB_TN

PEX_L0_SOC_SB_TP

PEX_L0_SOC_SB_TN

PEX_CAL_VSS

5

R501

200 OHM

1%

CH

402

4

1

C217

2

0.22 UF 10%

10 V

201

EMPTY

1

C53

2

0.22 UF 10%

10 V

X5R

201

1

C1087

2

0.22 UF

10%

10 V

X5R

1

201

C1083

2

0.22 UF

10%

10 V

X5R

201

1

C1081

2

0.22 UF 10%

10 V

X5R

201

1

C1067

2

0.22 UF

10%

10 V

X5R

201

1

C649

2

0.22 UF 10%

10 V

X5R

201

1

C629

2

0.22 UF 10%

10 V

X5R

201

3

1

C215

0.22 UF

10 V

2

10%

201

1

EMPTY

C48

0.22 UF

2

10%

10 V

X5R

201

1

2

C1085

0.22 UF 10%

10 V

201

X5R

1

2

C1082

0.22 UF 10%

10 V

201

X5R

1

2

C1080

0.22 UF 10%

10 V

201

X5R

1

2

C1068

0.22 UF 10%

10 V

201

X5R

1

C637

0.22 UF

10 V

2

10%

X5R

1

201

C658

2

0.22 UF

10 V

10%

X5R

3

201

MICROSOFT

2

PEX_SOC_SPARE_TP_C

PEX_SOC_SPARE_TN_C

PEX_SOC_ENET_TP_C

PEX_SOC_ENET_TN_C

PEX_L1_SOC_CFX_TP_C

PEX_L1_SOC_CFX_TN_C

PEX_L0_SOC_CFX_TP_C

PEX_L0_SOC_CFX_TN_C

PEX_L1_SOC_M2_TP_C

PEX_L1_SOC_M2_TN_C

PEX_L0_SOC_M2_TP_C

PEX_L0_SOC_M2_TN_C

PEX_L1_SOC_SB_TP_C

PEX_L1_SOC_SB_TN_C

PEX_L0_SOC_SB_TP_C

PEX_L0_SOC_SB_TN_C

PROJECT NAME

CONFIDENTIAL

Stockton

2

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PAGE

2/76

31

31

38

38

38

38

41

41

41

41

23

23

23

23

CSA

PAGE

2/76

1

1

FAB

C

VER

0.12

D

C

B

A

D

C

B

A

8

8

7

7

35

35

35

35

35

35

35

35

35

35

35

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

IN

1

2

R557

200 OHM

1%

CH

402

6

6

TMDS_TX_DP2

TMDS_TX_DN2

TMDS_TX_DP1

TMDS_TX_DN1

TMDS_TX_DP0

TMDS_TX_DN0

TMDS_TX_